Arteris, Inc. introduces new tiling and mesh topology capabilities in its NoC IP products, promising to enhance AI and machine learning compute performance by over tenfold for system-on-chip designs.
Arteris, Inc., a prominent player in the field of system intellectual property (IP), has unveiled a significant advancement in its network-on-chip (NoC) intellectual property offerings. The company, listed on Nasdaq under the ticker AIP, announced the integration of tiling capabilities and extended mesh topology support within its NoC IP products. This development promises to revolutionise the creation and development of system-on-chip (SoC) designs, specifically targeting enhancements in Artificial Intelligence (AI) and Machine Learning (ML) compute capabilities.
The newly introduced functionalities are expected to accelerate compute performance by over tenfold, catering to the growing demands of complex AI systems, without compromising project schedules, power efficiency, performance, and area (PPA) objectives. Tiling, a novel trend in SoC design, employs Arteris’ established NoC IP to streamline scaling processes, reduce design time, expedite testing, and mitigate design risk. This approach facilitates the creation of modular, scalable SoCs through the replication of soft tiles across the chip, each functioning as a standalone unit, which simplifies integration, verification, and optimisation.
Arteris’ flagship NoC IP products, FlexNoC and Ncore, incorporate these tiling and mesh topology features to adeptly manage the increase in AI compute within SoCs. As AI-powered systems expand in both size and complexity, these innovations allow for seamless scalability with merely the addition of soft tiles, thereby enhancing the SoC’s capabilities without necessitating extensive redesigns. Collectively, the utilisation of tiling and mesh topologies is projected to halve both the auxiliary processing unit (XPU) subsystem design time and the overall SoC connectivity execution time, in contrast to manually integrated, non-tiled designs.
The initial phase of NoC tiling arranges network interface units (NIUs) into modular, replicable blocks, thereby boosting the scalability, efficiency, and reliability of SoC designs. These advancements lead to the creation of larger, more sophisticated AI compute systems that adeptly manage the demands of rapidly evolving AI workloads across various domains. These domains include Vision, Machine Learning (ML) models, Deep Learning (DL), and Natural Language Processing (NLP), encompassing Large Language Models (LLMs) and Generative AI (GAI), for both training and inference purposes, including at edge computing levels.
Srivi Dhruvanarayan, Vice President of Hardware Engineering at SiMa.ai, remarked on the benefits of the collaboration with Arteris, stating, “Thanks to Arteris’ highly scalable and flexible mesh-based NoC IP, our SoC team has implemented support for larger AI data volumes and complex algorithms more efficiently.” He emphasised the creation of an Arm-based, multi-modal, software-centric edge AI platform that supports a diverse range of models, from Convolutional Neural Networks (CNNs) to multimodal Generative AI.
K. Charles Janac, President and CEO of Arteris, expressed enthusiasm about the enhancement in SoC design technology brought about by this innovation. He highlighted how these advancements equip existing customers who are developing cutting-edge AI-powered SoCs with the tools to expedite the development of significantly larger and more intricate AI systems while adhering to their project timelines and PPA benchmarks.
This announcement marks a notable progression in the SoC design landscape, offering both current and prospective users of Arteris’ products a pathway to more efficient and scalable AI implementations in their systems. As AI technology continues to evolve, the incorporation of such innovative IP solutions could play a pivotal role in supporting the industry’s growth and adaptation to increasingly complex computational demands.
Source: Noah Wire Services
